Conventionally, as a substrate for a device, an SOI wafer in which a silicon active layer (an SOI layer) is formed on a support substrate has been widely utilized. As a method for producing such an SOI wafer, for example, it is known that there are a SIMOX (Separation by Ion-Implanted Oxygen) method in which oxygen is implanted into a silicon wafer to form a silicon active layer insulated by an oxide film, and a bonding method in which two wafers are bonded together via an oxide film or directly.
In the SIMOX method, oxygen ions are implanted inside a silicon wafer from one of the main surfaces of the wafer that was subjected to mirror polishing and the like, to form oxygen ions implanted layer. Then, the wafer is subjected to heat-treatment, for example, under an inert gas atmosphere with temperature of 1300° C. or more, to transform the oxygen ions implanted layer formed inside the wafer into a buried oxide film layer (an insulator film layer). Thereby, an SOI wafer that is insulated by the insulator film layer in one wafer is obtained.
In addition, in an ion implantation delamination method which is one of the bonding methods, an insulator film such as an oxide film (also refers to as a buried insulator film or inter-layer insulator film) is formed on a surface of a silicon wafer (a bond wafer) to be a silicon active layer or on a surface of a silicon wafer (a base wafer) to be a support substrate, and an ion-implanted layer (a micro bubble layer) is formed inside the bond wafer by implanting ions such as hydrogen from one side surface of the bond wafer. Further, after the ion-implanted surface of the bond wafer is bonded to the base wafer via the oxide film, the bond wafer is delaminated at the ion-implanted layer as a boundary by heat treatment. Thereby, an SOI wafer in which a thin silicon active layer is formed over the base wafer via the oxide film can be obtained.
Further, there are also some cases that an insulator support substrate is used and a bond wafer is bonded to this directly, i.e., without an oxide film.
Further, after delaminating the bond wafer at the ion-implanted layer as a boundary, there are also some cases that heat treatment (bonding heat treatment) for making bonding strength between the silicon active layer and the base wafer sufficient, or cleaning with hydrofluoric acid for removing an oxide film on the surface is performed.
In the case of producing an SOI wafer as described above, as a silicon wafer, it has been conventional to use a silicon wafer on the surface of which micro pit defects with a size of 50 nm or more existed. However, in recent years, the demand for thinning the silicon active layer and the buried oxide film increases, and the demand for quality of a silicon wafer applicable to this has also become strict.
Especially, in the method for producing an SOI wafer such as the ion implantation delamination method, there are also some cases that cleaning with hydrofluoric acid for removing an oxide film on the surface is performed. At that time, there occurs many failures that the size of the micro pit defects existing on the surface of the silicon active layer is further enlarged by etching, the buried oxide film is etched by hydrofluoric acid infiltrated through the pit and the silicon active layer or the buried oxide film is destroyed almost entirely or partially.
Then, in order to reduce defects in the silicon active layer, there has been proposed the use of an epitaxial layer, a DZ (Denuded Zone) layer of an IG wafer or a silicon single crystal in so-called a neutral region (N region) where there exist no defects caused during growth of the single crystal which is called grown-in defects such as FPD, LSTD and COP.
For example, there has been proposed a method for producing an SOI wafer by forming an epitaxial layer on a silicon wafer (a bond wafer), implanting boron ions into the epitaxial layer, subsequently bonding the wafer to a support substrate via an oxide film, and further grinding and polishing the back surface of the bond wafer (for example, see Japanese Patent Laid-open (Kokai) No. 10-79498).
However, in the case of using the wafer on which the epitaxial layer is formed as the bond wafer as described above, defects in the silicon active layer can be improved, but there has been a problem that the production cost remarkably increases because the process for growing the epitaxial layer is added.
On the other hand, as a bond wafer, in the case of using a silicon wafer grown in N region where no micro defect such as FPD and COP exists, although it is required to accurately control growth conditions of a silicon single crystal, there is an advantage that the process for forming the epitaxial layer is not needed.
A method for producing a silicon single crystal will be explained herein, and then grown-in defects and N region will be explained.
As a method for producing a silicon single crystal, Czochralski Method (referred to as CZ method for short hereafter) is mainly used.
When producing a single crystal by CZ method, for example, an apparatus 10 for producing a single crystal as shown in FIG. 2 is used to produce the single crystal. This apparatus 10 for producing a single crystal has a member for containing and melting a polycrystalline material such as silicon, heat insulation members to insulate heat, and etc. They are installed in a main chamber 11. A pulling chamber 12 extending upwardly is continuously provided from a ceiling portion of the main chamber 11, and a mechanism (not shown) for pulling a single crystal 13 by a wire 14 is provided above it.
In the main chamber 11, a quartz crucible 16 for containing a melted raw material melt 15 and a graphite crucible 17 supporting the quartz crucible 16 are provided, and these crucibles 16 and 17 are supported by a shaft 18 so that they can be rotated and moved upwardly or downwardly by a driving mechanism (not shown). To compensate for decline of the melt level of the raw material melt 15 caused by pulling of the single crystal 13, the driving mechanism for the crucibles 16 and 17 is designed to rise the crucibles 16 and 17 as much as the melt level declines.
And, a graphite heater 19 for melting the raw material is provided so as to surround the crucibles 16 and 17. A heat insulating member 20 is provided outside the graphite heater 19 so as to surround it in order to prevent that the heat from the graphite heater 19 is directly radiated on the main chamber 11.
Moreover, a graphite cylinder 23 is provided above the crucibles, and a heat insulating material 24 is provided on the outside of the lower end of the graphite cylinder 23 so as to oppose to the raw material melt 15 so that the heat radiation from the melt surface is intercepted and the temperature of the raw material melt surface is kept.
A raw material lump is put in the quartz crucible 16 installed in the apparatus for producing a single crystal as described above, the crucible 16 is heated by the graphite heater 19 as described above to melt the raw material lump in the quartz crucible 16. A seed crystal 22 fixed by a seed holder 21 connected with the lower end of the wire 14 is immersed into the raw material melt 15 melted from the raw material lump as described above. Thereafter, the single crystal 13 having a desired diameter and quality is grown under the seed crystal 22 by rotating and pulling the seed crystal 22. In this case, after bringing the seed crystal 22 into contact with the raw material melt 15, so-called necking, once forming a neck portion by narrowing the diameter to about 3 mm, is performed, and then, a dislocation-free crystal is pulled by spreading to a desired diameter.
Next, grown-in defects and N region will be explained.
It is known that in the case of changing a growth rate F from high rate to low rate in the direction of a crystal growth axis in a CZ pulling apparatus with a usual furnace structure (hot zone: HZ) having a large G which is an average value of a temperature gradient in the crystal along a pulling axis from the melting point of silicon to 1400° C., a defect distribution diagram as shown in FIG. 4 can be obtained.
In FIG. 4, V region is a region that contains a large amount of vacancies, i.e., depressions, pits, or the like caused by lack of silicon atoms, and I region is a region that contains a large amount of dislocations or clusters of excess silicon atoms caused by existence of excess silicon atoms. It has also been confirmed that there exists a neutral (hereinafter occasionally abbreviated as N) region that contains no (or little) lack or excess of the atom between V region and I region, and defects called OSF (Oxidation Induced Stacking Fault) are distributed in a ring shape (hereinafter occasionally referred to as OSF ring) near a boundary of V region when observed in the cross section perpendicular to a crystal growth axis.
When the growth rate is relatively high, there exist grown-in defects such as FPD, LSTD and COP, which are considered due to voids consisting of agglomerated vacancy-type point defects, at a high density over the entire radial direction of the crystal, and the region containing these defects becomes V region. Further, along with lowering of the growth rate, the OSF ring is generated from the periphery of the crystal. There exist at a low density outside the OSF ring, L/D (Large Dislocation: an abbreviation for interstitial dislocation loop, such as LSEPD, LFPD and the like) defects (huge dislocation clusters) which are considered due to dislocation loops consisting of agglomerated interstitial silicon atoms, and the region where these defects exist becomes I region (occasionally referred to as L/D region). When the growth rate is further lowered, the OSF ring shrinks to the center of the wafer and disappears, so that the entire plane becomes I region.
N region located between the V region and the I region and outside the OSF ring becomes a region containing no FPD, LSTD and COP to be generated due to voids as well as no LSEPD and LFPD to be generated due to interstitial silicon atoms. In addition, it has been recently found that when further classifying N region, as shown in FIG. 4, there exist Nv region (the region where a lot of vacancies exist) adjacent to the outside of OSF ring and Ni region (the region where a lot of interstitial silicon atoms exist) adjacent to I region, and that when performing thermal oxidation treatment, a lot of oxygen precipitates are generated in the Nv region and little oxygen precipitates are generated in the Ni region.
Although such an N region conventionally existed only in a part of a plane of wafer, a crystal having N region over the entire radial plane (the entire plane of a wafer) has been able to be manufactured by controlling F/G that is a ratio of a pulling rate (F) to an average value (G) of a temperature gradient in the crystal along a pulling axis from the melting point of silicon to 1400° C.
Also, in the manufacture of an SOI wafer, as described above, there has been proposed a method in which a silicon single crystal wafer having N region over the entire surface is used as a bond wafer.
For example, there has been proposed an SOI wafer wherein a silicon single crystal is pulled by controlling a ratio (F/G) of the pulling rate F to the average value G of a temperature gradient in the crystal along a pulling axis from the melting point of silicon to 1400° C. within a predetermined range when it is pulled by Czochralski method (CZ method), and the silicon wafer in N region is used as a bond wafer (for example, see Japanese Patent Laid-open (Kokai) No. 2001-146498 and Japanese Patent Laid-open (Kokai) No. 2001-44398).
However, when a silicon single crystal in N region is pulled by CZ method with controlling the pulling rate and the like, this silicon single crystal in N region is grown in a range of a relatively limited pulling rate. Thus, there occurs a problem that it is difficult to control the pulling rate and productivity and yield of the single crystal become low. Therefore, an SOI wafer using such a single crystal in N region becomes relatively expensive.
On the other hand, as to a base wafer, it is originally required for supporting a silicon active layer via an insulator film, thus, no device is directly formed on a surface of the base wafer.
Therefore, as a base wafer, considering improvements of productivity etc., a silicon wafer that is produced by growing a silicon single crystal occupied by V region or partially OSF region and Nv region with high pulling rate as shown in FIG. 4, and then being processed to have a mirror surface from the above silicon single crystal grown with high pulling rate has been widely used. For example, there has been proposed to use a dummy-grade silicon wafer of which resistivity and the like do not meet product standards as a base wafer (for example, see Japanese Patent Laid-open (Kokai) No. 11-40786).
However, thinning of an inter-layer insulator film has been recently demanded, thus improving quality of a silicon wafer used as a base wafer has been demanded. That is, in the case that a thickness of an inter-layer insulator film is thick enough, there is no need to care about influences leading to dielectric breakdown even if vacancy defects like COPs that voids have grown are formed on a surface of a base wafer with high density. However, in the case that an inter-layer insulator film has a thin thickness of 100 nm or less, it is concerned that quality of the inter-layer insulator film may be deteriorated and insulation function may be in trouble.
Further, as a method for providing an SOI wafer at lower cost that is prone to be expensive, there has been proposed a method in which a delaminated wafer that is delaminated from a silicon active layer by ion implantation delamination method is reused as a base wafer (see Japanese Patent Laid-open (Kokai) No. 11-297583). However, as it has been recently demanded, in the case that an inter-layer insulator film of an SOI wafer has a thin thickness of, for example, 100 nm or less, if a delaminated wafer to be reused as a base wafer includes regions like V region, OSF region and huge dislocation clusters (LSEPD, LFPD), quality of the inter-layer insulator film comes to be deteriorated and insulation function becomes insufficient. Therefore, in this case, it is difficult to reuse as a base wafer.